1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device provided with a power supply circuit that generates an internal power supply voltage with a charge pumping operation.
2. Description of the Background Art
Currently, a burn-in test is conducted in a dynamic random access memory (DRAM) for the purposes of screening of a defective chip and evaluation of reliability. In a conventional burn-in test, such screening of the potential defective chip has been conducted by applying a high voltage to a chip operating in a high-temperature atmosphere to accelerate degradation of the defective portion.
In the generations on and after 0.25 xcexcm, however, it has become impossible to apply a voltage high enough to allow thorough screening of defects in oxide films while a device after molding is in operation, because of the problem of reliability of a transistor including resistance to hot carrier. Therefore, it is common at present to perform the burn-in test in two stages, as a wafer level burn-in test and a regular burn-in test.
In the wafer level burn-in test, a defective chip potentially including a defect in the oxide film is screened by statically applying a stress voltage to the chip in the wafer state for a relatively short period of time, to accelerate elicitation of the defect. In the regular burn-in test being performed after molding, operational reliability is evaluated in the device level, by applying a high voltage in a high-temperature atmosphere over a long period of time.
In the DRAM, evaluation of the oxide film breakdown voltage is particularly necessary for a switching transistor of a memory cell and a switching transistor within a data line separating circuit, since a high gate-source voltage would be applied to these switching transistors.
FIG. 9 is a schematic diagram showing a configuration of a memory cell of a DRAM. In FIG. 9, one-element type DRAM cell is illustrated.
Referring to FIG. 9, the memory cell 10 includes a capacitor 11 storing data in the form of charges and a switching transistor 12. The gate of switching transistor 12 is connected to a word line WL. In response to activation of word line WL, switching transistor 12 electrically connects a data line DL to one electrode (storage node) of capacitor 11. The other electrode (cell plate electrode) of capacitor 11 is supplied with a cell plate voltage Vcp.
When word line WL is selected and set to an active state (high level), switching transistor 12 turns on, and the data stored in capacitor 11 is read out on data line DL.
Hereinafter, binary signal and voltage levels will be referred to as a high level and a low level, which will be expressed as xe2x80x9cH levelxe2x80x9d and xe2x80x9cL levelxe2x80x9d, respectively.
A boosted voltage VPP is employed as a voltage corresponding to the active state of word line WL, such that a sufficient signal voltage is read out to data line DL despite the influence of the threshold voltage of the switching transistor being an NMOS transistor.
Specifically, a gate-source voltage of at most a VPP level is applied to a gate oxide film of switching transistor 12 when turned on. This makes switching transistor 12 more susceptible to a defect than the other portions.
Thus, in the wafer level burn-in test, a static stress voltage (hereinafter, also simply referred to as xe2x80x9cstressxe2x80x9d) is applied to the oxide film of switching transistor 12, while fixing the level of word line WL to the boosted voltage VPP, to screen a potential defect therein. The explanation above also applies to the switching transistor within the data line separating circuit.
FIG. 10 is a circuit diagram showing a configuration of the data line separating circuit.
Referring to FIG. 10, the data line separating circuit 20 is arranged to allow a sense amplifier to be shared by bit lines placed on its either side, for reduction of a chip area.
Data line separating circuit 20 includes a sense amplifier 21 and switching transistors 23-28.
Sense amplifier 21 is shared by bit line pairs BLPL and BLPR located at its respective sides, and amplifies a voltage difference between sense nodes Ns and /Ns. Bit line pair BLPL includes bit lines BLL and /BLL for transmission of data complementary to each other. Likewise, bit line pair BLPR includes bit lines BLR and /BLR for transmission of data complementary to each other.
Switching transistor 23 is electrically connected between bit line BLL and sense node Ns. Switching transistor 24 is electrically connected between bit line /BLL and sense node /Ns. Switching transistor 25 is electrically connected between bit line BLR and sense node Ns, and switching transistor 26 is electrically connected between bit line /BLR and sense node /Ns.
Switching transistors 23 and 24 have their gates receiving a control signal BLIL that is activated to an H level when the bit line pair on the left side is selected. Likewise, switching transistors 25 and 26 have their gates receiving a control signal BLIR activated to an H level when the bit line pair on the right side is selected.
Data line separating circuit 20 further includes switching transistors 27 and 28 for connecting sense nodes Ns and /Ns to a data input/output line pair DIOP.
Switching transistor 27 is electrically connected between sense node Ns and a line DIO that is one of the complementary data input/output lines constituting the data input/output line pair DIOP. Switching transistor 28 is electrically connected between sense node /Ns and a line /DIO that is the other of the complementary data input/output lines. Switching transistors 27 and 28 have their gates receiving a control signal CS that is activated to an H level according to a result of column selection.
In such a data line separating circuit, a voltage of the boosted voltage VPP level is applied to the gates of switching transistors 23-28 such that the data of an H level can be read/written with respect to the bit lines or the data input/output lines at a sufficient signal voltage. Specifically, control signals BLIL, BLIR and CS are each set to the boosted voltage VPP at the time of an H level (of an active state).
Accordingly, a gate-source voltage of at most the VPP level is applied to the gate oxide films of switching transistors 23-28. Thus, in the wafer level burn-in test, it is necessary to conduct screening of potential defects of switching transistors 23-28, as in the case of the switching transistor within the memory cell, by applying constant stress to the oxide films thereof.
Boosted voltage VPP used as the ON voltage of these switching transistors is usually generated by a boosting circuit with a charge pumping operation.
FIG. 11 is a circuit diagram showing a configuration of a common boosting circuit as an example of the power supply circuit conducting the charge pumping operation. Shown in FIG. 11 is a so-called single boost type boosting circuit.
Referring to FIG. 11, the boosting circuit 30 includes a ring oscillator 31, N channel MOS transistors 32-35, MOS capacitors 36-38, and a clock transmission circuit 40. Clock transmission circuit 40 includes inverters 41-47. Hereinafter, N channel MOS transistor and P channel MOS transistor will be simply referred to as xe2x80x9cNMOS transistorxe2x80x9d and xe2x80x9cPMOS transistorxe2x80x9d, respectively.
Ring oscillator 31 generates a pump clock PCLK having constant periods to a node N1. Inverters 43 and 47 transmit pump clock PCLK in phase to a node N2. Inverters 42 and 46 transmit pump clock PCLK in phase to a node N3. Inverters 41, 44 and 45 transmit pump clock PCLK in opposite phase to a node N4.
MOS capacitor 36 is coupled between nodes N2 and N5. MOS capacitor 37 is coupled between nodes N3 and N6. MOS capacitor 38 is coupled between nodes N4 and N7. MOS capacitors 36-38 are used to conduct the charge pumping operation.
NMOS transistor 35 is electrically connected between a power supply voltage VDD and node N7, and has its gate coupled to power supply voltage VDD. NMOS transistor 33 is electrically connected between power supply voltage VDD and node N5. NMOS transistor 34 is electrically connected between power supply voltage VDD and node N6. NMOS transistors 33 and 34 have their gates coupled to node N7.
NMOS transistor 32 is electrically connected between a node Np for supplying boosted voltage VPP and node N5, and has its gate coupled to node N6.
An operation of boosting circuit 30 will now be described.
When pump clock PCLK generated to node N1 by ring oscillator 31 is at an H level, node N5 is boosted by MOS capacitor 36. Likewise, node N6 is boosted by MOS capacitor 37, so that the gate of transistor 32 is boosted. As a result, the charges of the boosted node N5 can be sent out to node Np.
When pump clock PCLK is at an L level, nodes N5 and N6 are both at an L level. At this time, node N7 is boosted by MOS capacitor 38. Correspondingly, NMOS transistors 33 and 34 are turned on, so that nodes N5 and N6 are charged to the power supply voltage VDD level.
In this manner, as pump clock PCLK alternates between H and L levels at constant periods, the boosted charges are supplied to node Np, so that boosted voltage VPP is generated.
As a boosting pump capacitor for use in the boosting circuit, a MOS capacitor is usually preferred to a parallel-plate type capacitor, as the MOS capacitor has a thinner film and is able to hold charges of a larger capacity in the comparative area.
In a negative-voltage generating circuit with a similar configuration for generating a negative voltage with the charge pumping operation, a MOS capacitor is again employed as the pump capacitor. The negative voltage generated is used to prevent a leakage current of, e.g., a switching transistor in a memory cell.
FIG. 12 is a circuit diagram showing a configuration of a common negative-voltage generating circuit as another example of the power supply circuit conducting the charge pumping operation.
Referring to FIG. 12, the negative-voltage generating circuit 50 includes a ring oscillator 51, PMOS transistors 52-55, MOS capacitors 56-58, and a clock transmission circuit 60. Clock transmission circuit 60 includes inverters 61-68.
Ring oscillator 51 generates a pump clock PCLK having constant periods to a node N11. Inverters 63, 66 and 68 transmit pump clock PCLK in opposite phase to a node N12. Inverters 62, 65 and 67 transmit pump clock PCLK in opposite phase to a node N13. Inverters 61 and 64 transmit pump clock PCLK in phase to a node N14.
MOS capacitor 56 is coupled between nodes N12 and N15. MOS capacitor 57 is coupled between nodes N13 and N16, and MOS capacitor 58 is coupled between nodes N14 and N17.
PMOS transistor 55 is electrically connected between a ground voltage VSS and node N17, and has its gate coupled to node N17. PMOS transistor 53 is electrically connected between ground voltage VSS and node N15, and PMOS transistor 54 is electrically connected between ground voltage VSS and node N16. PMOS transistors 53 and 54 have their gates coupled to node N17.
PMOS transistor 52 is electrically connected between a node Nb for supplying a negative voltage VBB and node N15, and has its gate coupled to node N16.
In negative-voltage generating circuit 50, as pump clock PCLK alternates between H and L levels at constant periods, negative charges are sent to node Nb, so that negative voltage VBB is generated.
Unlike a normal MOS transistor, the MOS capacitor employed in the power supply circuit conducting the charge pumping operation, such as the boosting circuit and the negative-voltage generating circuit described above, requires a gate oxide film having a wide area to ensure a certain volume of capacity.
Each memory cell includes a MOS switching transistor. This MOS switching transistor has an extremely small gate area compared to the MOS capacitor for the charge pumping operation. In general, the gate area of one MOS capacitor for the charge pumping operation is approximately 1,000,000 times as large as the gate area of one MOS switching transistor.
Although these MOS elements different in function have MOS structures, the MOS capacitor for the charge pumping operation having such a huge gate oxide film area is much likely to suffer a defect due to a dust attached thereto or the like. If the oxide film of the MOS capacitor for the charge pumping operation actually suffers the defect, a normal function of the power supply circuit itself cannot be expected. Thus, there is a great necessity of screening such a potential defect.
In a conventional wafer level burn-in test, however, the voltage (stress) being applied to the MOS capacitor was not specified, so that the gate-source voltage of the MOS capacitor would vary during the test. With such a conventional burn-in test, sufficient screening of a potential defect for evaluation of the oxide film breakdown voltage was impossible.
In a regular burn-in test, unlike the case of the wafer level burn-in test in which a load is statically applied in a high-temperature atmosphere for a short period of time, a load would be applied at high temperature over a long period of time. Thus, the MOS capacitor having a large oxide film area was likely to suffer oxide film breakdown due to excessive stress applied thereto, so that there was a possibility that even those within a tolerance level would be misjudged as defective.
An object of the present invention is to provide a semiconductor device capable of setting stress being applied in a burn-in test to a MOS capacitor within a power supply circuit conducting a charge pumping operation.
The semiconductor device according to the present invention includes a power supply circuit that generates an internal power supply voltage by a charge pumping operation. The power supply circuit includes an oscillator generating a clock having constant periods, a pump capacitor having an oxide film that is formed between a first node and a second node, and a pump capacitor input control unit provided between the oscillator and the first node. The pump capacitor input control unit fixes a voltage of the first node such that a prescribed voltage is applied between the second node clamped to a first voltage and the first node in a burn-in test.
Preferably, the pump capacitor input control unit transmits a signal based on the clock to the first node in a normal operation.
Preferably, in the burn-in test conducted at a wafer level, the prescribed voltage is set such that stress of a desired level is applied to the oxide film.
Still preferably, in the burn-in test conducted after package molding, the prescribed voltage is set such that the stress being applied to the oxide film is restricted to a prescribed level.
Preferably, the pump capacitor input control unit sets the voltage of the first node to different levels in the burn-in test conducted at the wafer level and in the burn-in test conducted after the package molding.
Specifically, the pump capacitor input control unit sets the voltage of the first node such that stress of a desired level is applied to the oxide film in the burn-in test conducted at the wafer level and the stress being applied to the oxide film is restricted to a prescribed level in the burn-in test conducted after the package molding.
Alternatively, the pump capacitor input control unit preferably includes a select switch for switching voltage setting of the first node in the burn-in test between a second voltage for applying stress of a desired level to the oxide film and a third voltage for restricting the stress being applied to the oxide film to a prescribed level.
Still preferably, the third voltage is approximately equal to the first voltage.
Alternatively, the select switch has a metal interconnection selectively formed between a third internal node and one of a first internal node set to a fourth voltage in the burn-in test and a second internal node set to a fifth voltage, and the pump capacitor input control unit selects the voltage setting of the first node in the burn-in test according to a voltage of the third internal node.
Still preferably, the prescribed voltage corresponds to a power supply voltage that is set higher in the burn-in test than in the normal operation.
Accordingly, the main advantage of the present invention is that it is able to apply stress of a desired level to the pump capacitor within the power supply circuit in the burn-in test. In particular, at the time of the wafer level burn-in test, static stress can be intentionally applied to the gate oxide film of the pump capacitor, to carry out the screening test for accelerating the potential defect. In the regular burn-in test, it is possible to intentionally restrict the stress being applied to the gate oxide film of the pump capacitor, so that the oxide film breakdown due to excessive stress applied thereto can be prevented.
In addition, by switching the coupling of the select switch, it is possible to selectively set as to whether to intentionally apply stress to the pump capacitor in the burn-in test.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.